add wave -position end  sim:/testbench/u_cpu/if_PCToIM
add wave -position end  sim:/testbench/u_cpu/if_Inst
add wave -position end  sim:/testbench/u_cpu/ctrl_ImmeSrc
add wave -position end  sim:/testbench/u_cpu/ext_Imme
add wave -position end  sim:/testbench/u_cpu/u_CtrlUnit/Condition
add wave -position end  sim:/testbench/u_cpu/ctrl_PCMuxSel
add wave -position end  sim:/testbench/u_cpu/ctrl_ASrc4
add wave -position end  sim:/testbench/u_cpu/ctrl_BSrc4
add wave -position end  sim:/testbench/u_cpu/u_ForwardUnit/EXE_DstReg
add wave -position end  sim:/testbench/u_cpu/u_ForwardUnit/MEM_DstReg
add wave -position end  sim:/testbench/u_cpu/rf_Data1
add wave -position end  sim:/testbench/u_cpu/rf_Data2
add wave -position end  sim:/testbench/clk
add wave -position end  sim:/testbench/rst
add wave -position end  sim:/testbench/u_cpu/u_ForwardUnit/FORWARDA
add wave -position end  sim:/testbench/u_cpu/exe_ALUOp
add wave -position end  sim:/testbench/u_cpu/u_ALU/A
add wave -position end  sim:/testbench/u_cpu/u_ALU/B
add wave -position end  sim:/testbench/u_cpu/alu_F
add wave -position end  sim:/testbench/u_cpu/exe_ASrc
add wave -position end  sim:/testbench/u_cpu/exe_BSrc
add wave -position end  sim:/testbench/u_cpu/wb_RegWE
add wave -position end  sim:/testbench/u_cpu/wb_DstVal
add wave -position end  sim:/testbench/u_cpu/wb_DstReg
add wave -position end  sim:/testbench/u_cpu/u_RegFile/R0
add wave -position end  sim:/testbench/u_cpu/u_RegFile/R1
add wave -position end  sim:/testbench/u_cpu/u_RegFile/R2
add wave -position end  sim:/testbench/u_cpu/u_RegFile/R3
add wave -position end  sim:/testbench/u_cpu/u_RegFile/R4
add wave -position end  sim:/testbench/u_cpu/u_RegFile/R5
add wave -position end  sim:/testbench/u_cpu/u_RegFile/R6
add wave -position end  sim:/testbench/u_cpu/u_RegFile/R7
add wave -position end  sim:/testbench/u_cpu/u_RegFile/SP
add wave -position end  sim:/testbench/u_cpu/u_RegFile/IH
